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ISLA224P
TABLE 1. CLKDIV PIN SETTINGS
Digital Outputs
CLKDIV PIN
AVSS
Float
AVDD
DIVIDE RATIO
2
1
4
Output data is available as a parallel bus in
LVDS-compatible(default) or CMOS modes. In either case, the data
is presented in double data rate (DDR) format. Figures 3 and 4
show the timing relationships for LVDS and CMOS modes,
respectively.
SNR = 20 log 10 ? ------------------- ?
(EQ. 1)
? 2 π f t ?
The clock divider can also be controlled through the SPI port,
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52 μ s to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t J ) and SNR is shown in Equation 1 and is
illustrated in Figure 34.
1
IN J
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA(default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode can be controlled through the SPI port, by
An external resistor creates the bias for the LVDS drivers. A 10k Ω ,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the ISLA224P25 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
100
95
90
85
80
75
70
65
60
55
tj = 100ps
tj = 10ps
tj = 0.1ps
tj = 1ps
14 BITS
12 BITS
10 BITS
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to <103mW while Sleep mode reduces power
dissipation to <19mW.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
50
1M
10M 100M
INPUT FREQUENCY (Hz)
FIGURE 34. SNR vs CLOCK JITTER
1G
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52μs
to regain lock at 250MSPS.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
sampling instant shown in Figure 3. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
NAPSLP PIN
AVSS
Float
AVDD
MODE
Normal
Sleep
Nap
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
20
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
FN7570.1
November 30, 2012
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相关PDF资料
ISPTPKIT
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